1. Field of the Invention
The present application relates generally to an improved data processing system and method. More specifically, the present application is directed to a virtual address based buffer to retain an association to a user space application that owns the buffer.
2. Background of the Invention
In the field of microprocessor based data processing systems, the use of industry standard I/O busses to improve the performance and expand the capabilities of the data processing systems is well known. Standardized I/O busses provide a mechanism for connecting a wide variety of peripheral devices to the host bus of a data processing system. Peripheral devices may include, for example, high speed network adapters, hard-disk controllers, graphics adapters, audio adapters, and a variety of other devices. Among the most prevalent of the industry standard I/O busses is the Peripheral Component Interface (PCI) bus. The PCI bus has evolved over the years from revision 2.0 introduced in 1992 operating at a bus frequency of 33 MHz, to revision 2.1 introduced in 1995 with a maximum bus frequency of 66 MHz, to revision 2.2 introduced in 1998 and incorporating features such as message interrupts. Under PCI Spec 2.2, PCI bridges support two types of transactions: posted transactions (including memory write cycles), which complete on the initiating bus before they complete on the target bus, and delayed transactions (including memory read requests and I/O and configuration read/write requests), which complete on the target bus before they complete on the initiating bus. A PCI device that initiates a delayed transaction must relinquish control of the local PCI bus and wait for the target device to return the requested data (in the case of a delayed read request) or a completion message (in the case of a delayed write request). Once the requested information has arrived, the requesting device must wait until it again receives control of the PCI bus in the normal course of operations before it can retrieve the information from the PCI bridge.
More recently, the PCI-X Addendum to Local Bus Specification Rev. 2.2 has been proposed as a means for further improving the performance of PCI busses. The PCI-X Addendum incorporates registered transactions that improve performance by permitting a PCI-X compatible bridge or I/O adapter to make decisions on every other clock cycle. In addition, PCI-X incorporates protocol enhancements such as the attribute phase and split transactions that allow more efficient use of the bus. PCI-X is fully backward compatible with conventional PCI systems such that conventional PCI adapters will work in PCI-X capable systems and PCI-X adapters will work in PCI systems. If a conventional PCI device is located on a PCI-X bus, however, all adapters on the bus must operate in conventional PCI mode regardless of whether they are PCI-X capable.
In known systems there are two types of PCI I/O adapters that connect to a PCI bus, I/O adapters that have memory registration capabilities, such as IB Host Channel Adapters (HCAs) or Internet Warp (iWARP) Remote Direct Memory Access (RDMA) enabled NICs, and I/O adapters that do not have memory registration capabilities, such as NICs, Small Computer System Interface (SCSI), and FC adapters. To provide memory on I/O adapters that do not have memory registration capabilities, host address translation and protection tables are used, such as a translation control entry (TCE) table or an input/output memory management unit (IOMMU), which is a memory management unit (MMU) that connects a DMA-capable I/O bus to the main memory.
For I/O adapters that do not contain a memory registration table, known mechanisms fail to retain an association of user space addresses to a specific application. That is, known systems fail to allow a virtual address based buffer to be registered on a peripheral component interconnect (PCI) host bridge and the registration to retain association with the user space application that owns the virtual address based buffer.